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Disambiguation of "Im, Jay"

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A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.

, , , , , , , , , , , , , , , , and . ESSCIRC, page 297-300. IEEE, (2016)

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Jay Jorgenson

Sylvain Jay

Bak Im

Klaus Jay

Emmanuel Jay

 

Other publications of authors with the same name

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies., , , , , , , , , and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET., , , , , , , , , and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET., , , , , , , , , and 7 other author(s). ESSCIRC, page 297-300. IEEE, (2016)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET., , , , , , , , , and 11 other author(s). ISSCC, page 116-118. IEEE, (2020)A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET., , , , , , , , and . ISSCC, page 68-70. IEEE, (2016)6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET., , , , , , , , , and 7 other author(s). ISSCC, page 114-115. IEEE, (2017)A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET., , , , , , , , , and . ISSCC, page 390-392. IEEE, (2018)