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Disambiguation of "Vivet, Pascal"

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Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications.

, , , , and . DATE, page 1185-1188. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Damien Vivet

Gabriel Vivet

Pascal Vogel

Pascal Häller

Pascal Schneider

 

Other publications of authors with the same name

3D NoC using through silicon Via: An asynchronous implementation., , , and . VLSI-SoC, page 232-237. IEEE, (2011)An Asynchronous Power Aware and Adaptive NoC Based Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling., , , and . J. Low Power Electron., 7 (2): 265-273 (2011)Fast and accurate power annotated simulation: Application to a many-core architecture., , , and . PATMOS, page 191-198. IEEE, (2013)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits., , , , , , , , , and 6 other author(s). IEEE Des. Test, 33 (3): 21-36 (2016)A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs., , , , , , , , and . ESSCIRC, page 138-141. IEEE, (2008)Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization., , , , , , , and . ISLPED, page 121-126. ACM, (2020)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes., , , , , , and . 3DIC, page 1-5. IEEE, (2016)2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures., , , , , and . ISVLSI, page 386-391. IEEE Computer Society, (2014)A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 49 (7): 1475-1486 (2014)