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Disambiguation of "Dickson, Timothy O."

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.

, , , , , and . IEEE J. Solid State Circuits, 47 (12): 3220-3231 (2012)

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Paul Dickson

Timothy Saunders

Timothy Sulo

Timothy Leung

Timothy Creech

 

Other publications of authors with the same name

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (4): 1214-1226 (2018)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 55 (1): 19-26 (2020)6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS., , and . ISSCC, page 118-119. IEEE, (2017)A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS., , , , , and . IEEE J. Solid State Circuits, 47 (12): 3220-3231 (2012)Towards a sub-2.5V, 100-Gb/s Serial Transceiver., , , , , , , , and . CICC, page 471-478. IEEE, (2007)A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS., , , , , , and . ISSCC, page 122-124. IEEE, (2019)The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks., , , , , , , , , and . IEEE J. Solid State Circuits, 41 (8): 1830-1845 (2006)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 28-29. IEEE, (2022)