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Disambiguation of "da Rosa Jr., Leomar S."

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Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.

, , , , , and . LASCAS, page 355-358. IEEE, (2016)

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Catarina Caetano da Rosa

Foued Jrad

Da Liu

Da Wang

Robert Jr Cramer

 

Other publications of authors with the same name

Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)DAG based library-free technology mapping., , , , and . ACM Great Lakes Symposium on VLSI, page 293-298. ACM, (2007)Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms., , , , , and . ACM Great Lakes Symposium on VLSI, page 407-410. ACM, (2008)SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling., , and . ACM Trans. Design Autom. Electr. Syst., 26 (2): 9:1-9:38 (2021)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)Improving the methodology to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2013)DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (7): 1239-1243 (2020)Area-Aware Design of Static CMOS Complex Gates., , , , and . NEWCAS, page 282-286. IEEE, (2018)Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults., , , and . ICECS, page 357-360. IEEE, (2018)Switch level optimization of digital CMOS gate networks., , , and . ISQED, page 324-329. IEEE Computer Society, (2009)