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Test point insertion in hybrid test compression/LBIST architectures., , , , и . ITC, стр. 1-10. IEEE, (2016)Design for low test pattern counts., , , , , , и . DAC, стр. 136:1-136:6. ACM, (2015)Test Time and Area Optimized BrST Scheme for Automotive ICs., , , , , , , , , и . ITC, стр. 1-10. IEEE, (2019)Isometric Test Data Compression., , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (11): 1847-1859 (2015)An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits., и . DSD, стр. 619-625. IEEE Computer Society, (2007)Isometric test compression with low toggling activity., , , , , , , и . ITC, стр. 1-7. IEEE Computer Society, (2014)At-speed scan test with low switching activity., , , и . VTS, стр. 177-182. IEEE Computer Society, (2010)An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits., и . ATS, стр. 73-78. IEEE, (2007)Minimal area test points for deterministic patterns., , , , , и . ITC, стр. 1-7. IEEE, (2016)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , и . ITC, стр. 1-8. IEEE, (2015)