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10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack., , , , , , , , , and . 3DIC, page 1-6. IEEE, (2009)3D integration technology for 3D stacked retinal chip., , , , , , and . 3DIC, page 1-4. IEEE, (2009)Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications., , , , , and . 3DIC, page TS5.2.1-TS5.2.5. IEEE, (2015)Development of via-last 3D integration technologies using a new temporary adhesive system., , , , and . 3DIC, page 1-4. IEEE, (2013)Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM., , , , , and . IRPS, page 4. IEEE, (2015)Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding., , , , , , and . 3DIC, page 1-5. IEEE, (2010)Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI., , , , , and . 3DIC, page 1-4. IEEE, (2011)Chip-level TSV integration for rapid prototyping of 3D system LSIs., , , , , , , , and . 3DIC, page 1-4. IEEE, (2011)Effects of mechanical stress and moisture on packaging interfaces., , , , , , and . IBM J. Res. Dev., 49 (4-5): 663-676 (2005)