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A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (7): 1783-1797 (2017)Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)ADC-based Wireline Transceiver.. CICC, стр. 1-89. IEEE, (2019)Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee., , и . ISSCC, стр. 124-125. IEEE, (2021)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET., , , , , , , , , и . VLSI Circuits, стр. 190-. IEEE, (2019)A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (12): 3486-3502 (2017)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface., , , , , , , , , и 10 other автор(ы). IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)