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A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.

, , , , , , , , , и . IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)

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Paul Dickson

Timothy Saunders

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Timothy Creech

 

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