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Disambiguation of "Shiga, Hitoshi"

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A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.

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Hitoshi Tamura

Hitoshi Endo

Hitoshi Abe

Hitoshi Yamada

Hitoshi Kawanaka

 

Other publications of authors with the same name

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput., , , , , , , , , and 25 other author(s). IEEE J. Solid State Circuits, 42 (1): 219-232 (2007)A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate., , , , , , , , , and 38 other author(s). IEEE J. Solid State Circuits, 44 (1): 195-207 (2009)A 113mm2 32Gb 3b/cell NAND flash memory., , , , , , , , , and 28 other author(s). ISSCC, page 242-243. IEEE, (2009)Wordline voltage generating system for low-power low-voltage flash memories., , , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 55-63 (2001)A CMOS bandgap reference circuit with sub-1-V operation., , , , , , and . IEEE J. Solid State Circuits, 34 (5): 670-674 (1999)A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate., , , , , , , , , and 38 other author(s). ISSCC, page 506-507. IEEE, (2008)A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology., , , , , , , , , and 32 other author(s). ISSCC, page 198-199. IEEE, (2011)A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology., , , , , , , , , and 32 other author(s). IEEE J. Solid State Circuits, 47 (1): 75-84 (2012)A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 35 (11): 1648-1654 (2000)