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At-speed scan test with low switching activity., , , и . VTS, стр. 177-182. IEEE Computer Society, (2010)Minimal area test points for deterministic patterns., , , , , и . ITC, стр. 1-7. IEEE, (2016)An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits., и . ATS, стр. 73-78. IEEE, (2007)On New Test Points for Compact Cell-Aware Tests., , , , , , , , , и . IEEE Des. Test, 33 (6): 7-14 (2016)Low capture power at-speed test in EDT environment., , , , , и . ITC, стр. 714-723. IEEE Computer Society, (2010)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , и . ITC, стр. 1-8. IEEE, (2015)Hardware Protection via Logic Locking Test Points., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating., , , и . Asian Test Symposium, стр. 267-272. IEEE Computer Society, (2011)Test point insertion in hybrid test compression/LBIST architectures., , , , и . ITC, стр. 1-10. IEEE, (2016)