Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.

E. Moghaddam, J. Rajski, S. Reddy, and J. Janicki. Asian Test Symposium, page 267-272. IEEE Computer Society, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Percilla Moghaddam

Elham Farvili

Elham Rostamian

Elham Farazdaghi

Huschang Elhami

Other publications of authors with the same name

At-speed scan test with low switching activity.E. Moghaddam, J. Rajski, S. Reddy, and M. Kassab. VTS, page 177-182. IEEE Computer Society, (2010)Minimal area test points for deterministic patterns.Y. Liu, E. Moghaddam, N. Mukherjee, S. Reddy, J. Rajski, and J. Tyszer. ITC, page 1-7. IEEE, (2016)An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits.E. Moghaddam, and S. Hessabi. ATS, page 73-78. IEEE, (2007)On New Test Points for Compact Cell-Aware Tests.C. Acero, D. Feltham, M. Patyra, F. Hapke, E. Moghaddam, N. Mukherjee, V. Neerkundar, J. Rajski, J. Tyszer, and J. Zawada. IEEE Des. Test, 33 (6): 7-14 (2016)Low capture power at-speed test in EDT environment.E. Moghaddam, J. Rajski, S. Reddy, X. Lin, N. Mukherjee, and M. Kassab. ITC, page 714-723. IEEE Computer Society, (2010)Embedded deterministic test points for compact cell-aware tests.C. Acero, D. Feltham, F. Hapke, E. Moghaddam, N. Mukherjee, V. Neerkundar, M. Patyra, J. Rajski, J. Tyszer, and J. Zawada. ITC, page 1-8. IEEE, (2015)Hardware Protection via Logic Locking Test Points.M. Chen, E. Moghaddam, N. Mukherjee, J. Rajski, J. Tyszer, and J. Zawada. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)Logic BIST With Capture-Per-Clock Hybrid Test Points.E. Moghaddam, N. Mukherjee, J. Rajski, J. Solecki, J. Tyszer, and J. Zawada. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.E. Moghaddam, J. Rajski, S. Reddy, and J. Janicki. Asian Test Symposium, page 267-272. IEEE Computer Society, (2011)Test point insertion in hybrid test compression/LBIST architectures.E. Moghaddam, N. Mukherjee, J. Rajski, J. Tyszer, and J. Zawada. ITC, page 1-10. IEEE, (2016)

BibSonomy

Disambiguation of "Moghaddam, Elham K."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.

Please choose a person to relate this publication to

Percilla Moghaddam

Elham Farvili

Elham Rostamian

Elham Farazdaghi

Huschang Elhami

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Moghaddam, Elham K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.

Please choose a person to relate this publication to

Percilla Moghaddam

Elham Farvili

Elham Rostamian

Elham Farazdaghi

Huschang Elhami

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.