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High efficiency data access system architecture for deblocking filter supporting multiple video coding standards., , , , and . IEEE Trans. Consumer Electronics, 58 (2): 670-678 (2012)A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications., , , , and . ACM Trans. Design Autom. Electr. Syst., 14 (1): 17:1-17:17 (2009)A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding., , and . APCCAS, page 312-315. IEEE, (2008)A dynamic quality-scalable H.264 video encoder chip., , , , , , and . ASP-DAC, page 125-126. IEEE, (2009)A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video., , , , , , , and . ASP-DAC, page 73-74. IEEE, (2011)A low-power management technique for high-performance domino circuits., , , , and . ASP-DAC, page 93-94. IEEE, (2011)An inter-frame/inter-view cache architecture design for multi-view video decoders., , , , , and . APSIPA, page 1-4. IEEE, (2012)A Dynamic Quality-scalable H.264 Video Encoder., , , , , , and . ISCAS, page 1932. IEEE, (2009)A 360-degree panoramic video system design., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A Multi-standard Video Decoder for High Definition Video Applications., , , , and . ISCAS, page 1933. IEEE, (2009)