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2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , и 18 other автор(ы). ISSCC, стр. 46-48. IEEE, (2020)Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-7. IEEE, (2013)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits., , , , , , , , , и 6 other автор(ы). IEEE Des. Test, 33 (3): 21-36 (2016)Heat spreading packaging solutions for hybrid bonded 3D-ICs., , , , , , , , , и 2 other автор(ы). 3DIC, стр. 1-6. IEEE, (2016)Influence of 3D integration on 2D interconnections and 2D self inductors HF properties., , , , , , и . 3DIC, стр. 1-6. IEEE, (2009)Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform., , , , , , , , , и 18 other автор(ы). OFC, стр. 1-3. IEEE, (2015)3D integration demonstration of a wireless product with design partitioning., , , , , , , , , и 17 other автор(ы). 3DIC, стр. 1-5. IEEE, (2011)Using TSVs for thermal mitigation in 3D circuits: Wish and truth., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-8. IEEE, (2014)First integration of Cu TSV using die-to-wafer direct bonding and planarization., , , , , , , , , и 3 other автор(ы). 3DIC, стр. 1-5. IEEE, (2009)RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits., , , , , , , , и . 3DIC, стр. 1-8. IEEE, (2013)